Registro completo de metadatos
| Campo DC | Valor | Lengua/Idioma |
|---|---|---|
| dc.creator | Cayssials, Ricardo Luis | - |
| dc.creator | Ferro, Edgardo Carlos | - |
| dc.creator | Urriza, José M. | - |
| dc.creator | Boemo, Eduardo | - |
| dc.date | 2017-01-24T18:53:45Z | - |
| dc.date | 2017-01-24T18:53:45Z | - |
| dc.date | 2013-08 | - |
| dc.date | 2017-01-19T19:53:30Z | - |
| dc.date.accessioned | 2019-04-29T15:54:57Z | - |
| dc.date.available | 2019-04-29T15:54:57Z | - |
| dc.identifier | Cayssials, Ricardo Luis; Ferro, Edgardo Carlos; Urriza, José M.; Boemo, Eduardo ; Real-Time Scheduling Architecture for Embedded Systems; Praise Worthy Prize; International Review on Computers and Software; 8; 8; 8-2013; 1843-1853 | - |
| dc.identifier | 1828-6003 | - |
| dc.identifier | http://hdl.handle.net/11336/11834 | - |
| dc.identifier | 1828-6011 | - |
| dc.identifier.uri | http://rodna.bn.gov.ar:8080/jspui/handle/bnmm/305250 | - |
| dc.description | Industrial applications require meeting real-time specifications. Real-time systems are implemented using processors in order to execute real-time tasks. Temporal constraints must be supported by real-time operating systems or designing the application based on specific hardware resources. Previous approaches to real-time processors have implemented operating system functions in hardware and consequently they are designed to manage tasks’ periods rather than real-time. They cannot be used in a great deal of applications because they are based on restrictive models. This paper proposes the Hardware Real-Time Scheduling Architecture (HRTSA) that introduces an innovative methodology with which to efficiently manage time, events, priorities and tasks in an embedded hardware implementation. The HRTSA is described and realtime performance is evaluated | - |
| dc.description | Fil: Cayssials, Ricardo Luis. Consejo Nacional de Investigaciones Científicas y Técnicas. Centro Científico Tecnológico Bahía Blanca. Instituto de Investigación en Ingeniería Eléctrica; Argentina. Universidad Nacional del Sur. Departamento de Ingenieria Electrica y de Computadoras; Argentina | - |
| dc.description | Fil: Ferro, Edgardo Carlos. Universidad Nacional del Sur. Departamento de Ingenieria Electrica y de Computadoras; Argentina. Consejo Nacional de Investigaciones Científicas y Técnicas; Argentina | - |
| dc.description | Fil: Urriza, José M.. Universidad Nacional de la Patagonia; Argentina | - |
| dc.description | Fil: Boemo, Eduardo . Universidad Autónoma de Madrid; España | - |
| dc.format | application/pdf | - |
| dc.format | application/pdf | - |
| dc.language | eng | - |
| dc.publisher | Praise Worthy Prize | - |
| dc.relation | info:eu-repo/semantics/altIdentifier/url/http://www.praiseworthyprize.org/jsm/index.php?journal=irecos&page=article&op=view&path%5B%5D=13396 | - |
| dc.rights | info:eu-repo/semantics/restrictedAccess | - |
| dc.rights | https://creativecommons.org/licenses/by-nc-sa/2.5/ar/ | - |
| dc.source | reponame:CONICET Digital (CONICET) | - |
| dc.source | instname:Consejo Nacional de Investigaciones Científicas y Técnicas | - |
| dc.source | instacron:CONICET | - |
| dc.subject | REAL-TIME SCHEDULING | - |
| dc.subject | FPGA | - |
| dc.subject | SOFT-PROCESSOR | - |
| dc.subject | MICROPORCESSOR DESIGN | - |
| dc.subject | Otras Ingeniería Eléctrica, Ingeniería Electrónica e Ingeniería de la Información | - |
| dc.subject | Ingeniería Eléctrica, Ingeniería Electrónica e Ingeniería de la Información | - |
| dc.subject | INGENIERÍAS Y TECNOLOGÍAS | - |
| dc.title | Real-Time Scheduling Architecture for Embedded Systems | - |
| dc.type | info:eu-repo/semantics/article | - |
| dc.type | info:eu-repo/semantics/publishedVersion | - |
| dc.type | info:ar-repo/semantics/articulo | - |
| Aparece en las colecciones: | CONICET | |
Ficheros en este ítem:
No hay ficheros asociados a este ítem.